Lab 7

Deadline: EOL (End of Lab) Friday, October 25th

Objectives:

  • TSWBAT analyze timing for circuits and design circuits.

Setup

Pull the Lab 7 files from the lab starter repository with

git pull starter master

All the work in this lab will be done from the digital logic simulation program Logisim Evolution, which is included in the lab starter files.

IMPORTANT: Please use the .jar file we’ve given you, not the version of Logisim that is downloaded on the lab computers! And a note: Logisim does not save your work as you go along, and it does not automatically create a new .circ file when you open it! Save when you start, and save frequently as you work.

You can open Logism via:

java -jar logisim-evolution.jar

IMPORTANT: Logism is a Java program that requires a GUI, so doing the lab over terminal won’t work (without window forwarding, detailed below). If you wish to work on the lab locally, ensure you have Java installed on your local machine, and pull the latest lab starter files to your local machine. Then, you should be open the program as above. If you wish to run the program over the terminal, you will need to add the -X flag to your SSH command to enable window forwarding (for example, ssh -X cs61c-[email protected]). On Windows machines, you may need to additionally install Xming.

Exercise 1 - Inefficiencies Everywhere

For this exercise, we can assume that registers initially carry the value zero. We will be using the lab file exercise1.circ, which should have a subcircuit called non_pipelined which looks something like this:

All this circuit does is take in two inputs, multiply them together, and then add the result to the current state value. For this circuit, let the propagation delay of an adder block be 50ns, the propagation delay of a multiplication block be 55ns, and the CLK-to-Q delay of a register be 5ns. Assuming no setup time and hold time, calculate the maximum clock rate at which this circuit can operate. Assume that both inputs come from clocked registers that receive their data from an outside source.

Checkpoint

  • At this point, make sure that you are comfortable with calculating clock rate using propagation delays and finding the critical path
  • Be ready to show your calculations to achieving the maximum clock rate for the non-pipelined circuit.

Exercise 2 - Mid Semester Survey

As part of the semester, we ask that you provide feedback for how the course is going. While we keep answers anonymous, we require that all students fill out the survey to receive credit for this lab. You can find the link here. All you need to show is the “You’ve already responded” page to receive credit for this portion.

Checkoff

There is no dedicated Lab Autograder assignment for this lab. Here are the checkoff requirements:

Exercise 1:

  • Show your calculations for the maximum clock rate for the non-pipelined circuit to your TA/AI.

Exercise 2:

  • Show that you have filled out the mid-semester survey.