Lab 13

Objectives:

• TSW explore the workings of virtual memory, specifically the TLB and the Page Table
• TSWBAT analyze TLB hit rate and Page Table hit rate and figure out what accesses optimize these values

Setup

For this lab we will mostly be using the virtual memory simulation features of Camera, a cache and virtual memory simulator. You may also find the cache simulations interesting, however we won’t be working with those here. Unfortunately, Camera is known to have issues when trying to run it on the instructional machines, so it’s recommend to download Camera from here, and simply double click on the jar file to run it on your own laptop. If you’re on a mac, you may need to go to “Security & Privacy” in your settings and click “open anyway” to allow Camera to run. Some displays don’t seem to play nice with the standard Camera app, if the values in memory are all squished together, try running this version of Camera.

Once Camera opens up, select the virtual memory option to open a visualization of the virtual memory system. In the top left you can see the contents of physical memory. Just below that is a listing of all the pages of virtual memory for this process. To the right of these items are the contents of the TLB and the Page Table. At this point these should all be empty as we haven’t done anything yet. Read about the statistics of your memory system in the “PROGRESS UPDATE” box at the bottom of the window. This area will keep you updated on your status through the simulation as it progresses. You can move the simulation forward, backward or start it over from the beginning using the buttons to the right of the “PROGRESS UPDATE” box.

Exercise 0 - Sanity Check

Before you continue, MAKE SURE THAT YOU OPENED THE VM SIMULATOR AND NOT THE CACHE SIMULATOR.

Exercise 1 - Working with Camera

Click the button labeled “Auto Generate Add. Ref. Str.” at the right-hand side of the window. This will generate a set of ten address references. You can think of these as a series of RISC-V “load word” instructions reading from the memory address specified. Click the button labeled “Next” to begin the simulation.

For the rest of this exercise you are at the mercy of the “PROGRESS UPDATE” box. After each click of the “Next” button examine the contents of the box and the current state of the memory system. Try to really get an understanding of what is going on in the TLB, the Page Table, and Physical Memory at each step.

Once you have reached the end of the simulation note the number of TLB Hits and Misses and Page Hits and Faults. Write these numbers down, along with the sequence of memory accesses used to show to your TA during checkoff.

Checkpoint

• How many TLB Hits and Misses did we have for the randomly generated set of ten addresses? What about for Page Hits and Faults?
• Did you have any Page Hits? Explain why. Can you think of a set of ten addresses that would result in a Page Hit?
• Explain the process by which we turn a virtual address into a physical address for the very first access (aka TLB Miss and Page Fault).

Exercise 2 - Misses

Checkpoint

• Demonstrate that your ten memory accesses results in ten TLB Misses and ten Page Faults. Explain why this behavior occurs.

Exercise 3 - Fixing our Faults

Given your sequence of memory accesses from Exercises 2, can you find a change to a single parameter (e.g. TLB size, page table size, memory size, etc…) that would result in the same number (ten) of TLB misses but result in fewer than ten page faults? Work through this on paper and be ready to show your results to your TA during checkoff.

Checkpoint

• Explain the single parameter change that would result in ten TLB misses, but fewer than ten page faults.

Exercise 4 - Bringing it All Together

VMSIM is another online virtual memory simulator. You have three options for this exercise.

• Go to the VMSIM website and inspect the VMSIM applet. On this site you can run the simulation, step through it, and reset it. However, this application may not run correctly on Chrome, so if you are running it on your home machine or on hive you should use Firefox. You may also run into security settings with Java. More about java security permissions can be found here
• If you are unable to open the link in your browser, you may also use the appletviewer command in terminal like so:
\$ appletviewer http://denninginstitute.com/workbenches/vmsim/vm.html

• Watch this webm of the simulation, and answer the questions using it.

What is different about the setup of the system in VMSIM as compared to CAMERA? In particular, what are P1, P2, P3, and P4? If you watch closely you’ll see that this simulation reports a much higher percentage of TLB misses than the random run on CAMERA did. Why might this be? (If you have trouble following the simulation, you can turn down the speed using the slider on the bottom right.)

Checkpoint

• Explain why there is a much higher percentage of TLB misses in this simulation.