Lab 08

Deadline: EOD (End of Day) Friday, July 24th


  • The student would explore the workings of virtual memory, specifically the TLB and the Page Table.
  • The student would be able to analyze TLB hit rate and Page Table hit rate and figure out what accesses optimize these values.


There is no starter code to pull. Follow the instructions below to download the software necessary to complete this lab.

For this lab we will mostly be using the virtual memory simulation features of Camera, a cache and virtual memory simulator. You may also find the cache simulations interesting, however we won’t be working with those here. Unfortunately, Camera is known to have issues when trying to run it on the Hive or Linux machines, so it’s recommend to download Camera from here, and simply double click on the jar file to run it on your own (non-Linux) laptop. If you’re on a Mac, you may need to go to “Security & Privacy” in your settings and click “Open Anyway” to allow Camera to run. Some displays don’t seem to play nice with the standard Camera app, if the values in memory are all squished together, try running this version of Camera. If you are unable to find a way to get Camera working on a machine, please partner up with someone who does.

Once Camera opens up, select the virtual memory option to open a visualization of the virtual memory system. In the top left you can see the contents of physical memory. Just below that is a listing of all the pages of virtual memory for this process. To the right of these items are the contents of the TLB and the Page Table. At this point these should all be empty as we haven’t done anything yet. Read about the statistics of your memory system in the “PROGRESS UPDATE” box at the bottom of the window. This area will keep you updated on your status through the simulation as it progresses. You can move the simulation forward, backward or start it over from the beginning using the buttons to the right of the “PROGRESS UPDATE” box.

Exercise 0 - Sanity Check


Exercise 1 - Working with CAMERA

Click the button labeled “Auto Generate Add. Ref. Str.” at the right-hand side of the window. This will generate a set of ten address references. You can think of these as a series of RISC-V “load word” instructions reading from the memory address specified. Click the button labeled “Next” to begin the simulation.

For the rest of this exercise you are at the mercy of the “PROGRESS UPDATE” box. After each click of the “Next” button examine the contents of the box and the current state of the memory system. Try to really get an understanding of what is going on in the TLB, the Page Table, and Physical Memory at each step.

Once you have reached the end of the simulation note the number of TLB Hits and Misses and Page Hits and Faults. Write these numbers down, along with the sequence of memory accesses used to show to your TA during checkoff.


  • Given the way the address was broken down, how big are the pages in this model?
  • How many TLB Hits and Misses did we have for the randomly generated set of ten addresses? What about for Page Hits and Page Faults?
  • Did you have any Page Hits? Explain why. Can you think of a set of ten addresses that would result in a Page Hit?
  • Explain the process by which we turn a virtual address into a physical address for the very first access (emphasizing on TLB Misses and Page Faults).

Exercise 2 - Misses

Now that you’ve seen what a random workload looks like in the VM system let’s try creating a custom workload with a specific property. Your goal for this exercise is to create a workload of ten memory accesses that will cause ten TLB misses and ten Page Faults. You should be able to come up with such a workload on paper, but then you should run it in CAMERA to verify your work. You can specify a custom workload in CAMERA by clicking the button labeled “Self Generate Add. Ref. Str.” and entering in the addresses you want to reference one at a time. When you are satisfied that you’ve got a valid sequence write it down and be ready to show it to your TA during checkoff.


  • Demonstrate that your ten memory accesses results in ten TLB Misses and ten Page Faults. Explain why such behavior occurs.

Exercise 3 - Fixing our Faults

Given your sequence of memory accesses from Exercise 2, can you find a change to a single parameter (e.g. TLB size, page table size, memory size, etc…) that would result in the same number (ten) of TLB misses but result in fewer than ten page faults? Work through this on paper and be ready to show your results to your TA during checkoff.


  • Explain the single parameter change that would result in ten TLB misses, but fewer than ten page faults.

Exercise 4 - Bringing it All Together

We used VMSIM, another Virtual Memory simulator, to create this question. You have two options for this exercise.

  • Watch this webm of a VMSIM simulation.
  • Use the appletviewer command in your Terminal like so (doesn’t work on Hive):
$ appletviewer 

Observe what is happnening and answer the following questions:

What is different about the setup of the system in this question as compared to the setup in CAMERA? In particular, what are P1, P2, P3, and P4? If you watch closely you’ll see that this simulation reports a much higher percentage of TLB misses than random runs on CAMERA did. Why might this be? (If you have trouble following the simulation, use the appletviewer and turn down the speed using the slider on the bottom right.)


  • Explain why there is a much higher percentage of TLB misses in this simulation


Similar to last week, there will be no autograded portion of this lab! Just be able to answer the following questions and explain them to your TA:

Exercise 0

  • None

Exercise 1

  • Explain the answers to the questions on TLB and Page hits and misses to the TA
  • Explain the process for turning a virtual address into a physical address for the very first memory access

Exercise 2

  • Demonstrate your memory accesses
  • Explain why this behavior occurs

Exercise 3

  • Explain the single parameter change

Exercise 4

  • Explain the much higher percentage of TLB misses